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Run Length Encoding in DSlogic

PostPosted: Sat Mar 14, 2015 5:26 am
by dpenev
Hi Guys,

Last few day sI spent with my DSLogic.
I have browsed all the PC side, firmware and HDL code and got some ide about the software structure
My main goal was to implement RLE and eventually to optimize the memory utilization of the instrument.
What I have done:
- I have implemented RLE encoding in the Verilog
- I have implemented RLE decoding in the /DSLogic/libsigrok4DSLogic
- tested successfully the above with 16M record length settings and 100MHz sampling rate and using 'Instant' triggering in the GUI

My implementation at the moment doesn't increase the 16M record.
Should be easy to be done but require GUI programming which at the moment I don't want to go into.

So what left for the initial goal checked:
- expand the shown by the GUI capture window in case of RLE (should be easy for GUI person).
- check box in the GUI to enable/disable RLE, for some signals RLE is not beneficial (easy)
- in case of RLE for some signals RLE is very efficient so we should wait a lot before filling the predefined RLE buffer.
So in this case the best is if ‘stop’ button shows up to the point signals are captured (easy)
- testing of the RLE using triggers, different record and sampling rates etc. (this may require some time, I hope DreamSorceLab can help? )

My code
https://github.com/dpenevdpenev/DSLogic
https://github.com/dpenevdpenev/DSLogic-hdl

As a note.
The hardware concept is perfect for LA as far as I can tell.
The HDL code however is very messy and very hard to be maintained.
If properly done it would be very good open source LA project!

In addition the internal HDL logic is relatively complex so I guess only a simple triggering can fit in the Sigrok LA API.

Best Regards
Dimitar Penev

Re: Run Length Encoding in DSlogic

PostPosted: Wed Apr 15, 2015 11:07 pm
by Andy
Hi dpenev,

Really thanks for your efforts on RLE.
We will integrated your improvement to our new repo:
https://github.com/DreamSourceLab/DSView

Thanks again!