RLE on DSLogic

Topics about DSLogic software development
I own both the DSLogic and the Open Workbench Logic Sniffer. Although the OWLS has only 216K onboard memory I find myself using it more often than the DSLogic because it has the ability to run length encode the samples and the ols client is able to switch between RLE and normal mode. At the expense on 1 channel you can get a much longer (timewise) capture. This is particularly useful when analyzing SPI, I2C or serial transmissions. For more complex captures I end up using my work Tektronix TLA. Even with the TLA with its huge memory I still use quite often the "store transitions only" so I think having something equivalent for the DSLogic would be very useful. Are there any plans to implement something like this (with a future FPGA image) ?
zelea2
 
Posts: 3
Joined: Wed Sep 10, 2014 11:07 pm

+1
Toley
 
Posts: 12
Joined: Sat Aug 30, 2014 1:15 am

+1

Lack of this feature is my biggest concern so far.....
maara
 
Posts: 5
Joined: Sun Jul 20, 2014 12:48 am

Thanks for your feedback.
We will consider this feature in next version.
Andy
Site Admin
 
Posts: 149
Joined: Fri Jul 11, 2014 9:20 am

Andy wrote:Thanks for your feedback.
We will consider this feature in next version.


Please do so as this is quite essential feature and the hw is strong enough to provide such feature...
maara
 
Posts: 5
Joined: Sun Jul 20, 2014 12:48 am

Hi Gents, DreamsourceLab

Since a while no new software updates haven been released.
DreamsourceLab, when the next update is planed for and what features are you planning to fix/add?
Do you plan to get RLE implemented in a near future?

I believe DSLogic is a great project so nice to be moved ahead.

RLE is something important in my opinion and at the same time something which should not be very complex to be done.
I don't have at the moment time enough to investigate the current HDL code,
but I am willing to spend some time.
I am having some Verilog experience already on a Xilinx devices.

Are there other people with Verilog/HDL knowledge interested in this work so we join the efforts?

Best Regards
Dimitar
dpenev
 
Posts: 12
Joined: Sat Dec 06, 2014 5:49 pm

Hi All,

Just to report the latest additions in my DSLogic-hdl branch https://github.com/dimitarpenev/DSLogic-hdl
-Synthesis from a command line using gmake
-Added Run Length Encoding (RLE)
-Test bench using Icarus Verilog. CPU interface is not fully tested.

You can test the RLE with the latest ASD DSLogic https://github.com/asanza/DSLogic.
Still the GUI shows only the first 16M samples of the RLE but this is to be expanded.
You need to define rising/falling triger condition and depending of your signal wait up to about 20 sec
to get the currently fixed RLE buffer fill.

Cheers
Dimitar
dpenev
 
Posts: 12
Joined: Sat Dec 06, 2014 5:49 pm

Hi dpenev,

Really thanks for all of your efforts on DSLogic.
We will integrate your RLE implement to our new update, and support this feature in our new GUI software:
https://github.com/DreamSourceLab/DSView

Thanks again!
Andy
Site Admin
 
Posts: 149
Joined: Fri Jul 11, 2014 9:20 am

Hi Andy,

It looks like the project rise from the dead. :)
Please keep going and please commit all even minor steps you do so anyone can follow the project evolution.

BTW what is the hardware diference between DSLogic and DSLogic pro?

Dimitar
dpenev
 
Posts: 12
Joined: Sat Dec 06, 2014 5:49 pm

dpenev wrote:Hi Andy,

It looks like the project rise from the dead. :)
Please keep going and please commit all even minor steps you do so anyone can follow the project evolution.

BTW what is the hardware diference between DSLogic and DSLogic pro?

Dimitar


The only difference between DSLogic and DSLogic Pro is the setting of threshold.
DSLogic only support two voltage threshold: 1.4v or 2v.
The threshold of DSLogic Pro can be set between 0 ~ 5v with 0.1v step.

Thanks.
Andy
Site Admin
 
Posts: 149
Joined: Fri Jul 11, 2014 9:20 am

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